<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="2.7.1" version="1.0">
This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
<lib desc="#Wiring" name="0"/>
  <lib desc="#Gates" name="1"/>
  <lib desc="#Plexers" name="2"/>
  <lib desc="#Arithmetic" name="3"/>
  <lib desc="#Memory" name="4">
    <tool name="ROM">
      <a name="contents">addr/data: 8 8
0
</a>
    </tool>
  </lib>
  <lib desc="#I/O" name="5"/>
  <lib desc="#Base" name="6">
    <tool name="Text Tool">
      <a name="text" val=""/>
      <a name="font" val="SansSerif plain 12"/>
      <a name="halign" val="center"/>
      <a name="valign" val="base"/>
    </tool>
  </lib>
  <main name="grnMem2"/>
  <options>
    <a name="gateUndefined" val="ignore"/>
    <a name="simlimit" val="1000"/>
    <a name="simrand" val="0"/>
  </options>
  <mappings>
    <tool lib="6" map="Button2" name="Menu Tool"/>
    <tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
    <tool lib="6" map="Button3" name="Menu Tool"/>
  </mappings>
  <toolbar>
    <tool lib="6" name="Poke Tool"/>
    <tool lib="6" name="Edit Tool"/>
    <tool lib="6" name="Text Tool">
      <a name="text" val=""/>
      <a name="font" val="SansSerif plain 12"/>
      <a name="halign" val="center"/>
      <a name="valign" val="base"/>
    </tool>
    <sep/>
    <tool lib="0" name="Pin">
      <a name="tristate" val="false"/>
    </tool>
    <tool lib="0" name="Pin">
      <a name="facing" val="west"/>
      <a name="output" val="true"/>
      <a name="labelloc" val="east"/>
    </tool>
    <tool lib="1" name="NOT Gate"/>
    <tool lib="1" name="AND Gate"/>
    <tool lib="1" name="OR Gate"/>
  </toolbar>
  <circuit name="grnMem2">
    <a name="circuit" val="grnMem2"/>
    <a name="clabel" val=""/>
    <a name="clabelup" val="east"/>
    <a name="clabelfont" val="SansSerif plain 12"/>
    <appear>
      <rect fill="none" height="45" stroke="#000000" stroke-width="2" width="60" x="50" y="55"/>
      <text font-family="SansSerif" font-size="12" text-anchor="middle" x="60" y="83">A</text>
      <text font-family="SansSerif" font-size="12" text-anchor="middle" x="100" y="84">V</text>
      <text font-family="SansSerif" font-size="12" text-anchor="middle" x="80" y="68">GrNMem</text>
      <text font-family="SansSerif" font-size="12" text-anchor="middle" x="80" y="82">2</text>
      <circ-port height="8" pin="290,240" width="8" x="46" y="76"/>
      <circ-port height="10" pin="630,240" width="10" x="105" y="75"/>
      <circ-anchor facing="east" height="6" width="6" x="67" y="97"/>
    </appear>
    <wire from="(500,240)" to="(630,240)"/>
    <wire from="(290,240)" to="(360,240)"/>
    <comp lib="0" loc="(290,240)" name="Pin">
      <a name="width" val="7"/>
      <a name="tristate" val="false"/>
    </comp>
    <comp lib="4" loc="(500,240)" name="ROM">
      <a name="addrWidth" val="7"/>
      <a name="dataWidth" val="32"/>
      <a name="contents">addr/data: 7 32
204e821 204e822 204e823 204e824 204e825 204e826 204e827 204e828
204e863 a04e821 a04e822 a04e823 a04e824 a04e825 a04e826 a04e827
a04e828 a04e829 a04e860 a04e861 a04e862 a04e863 a04e864 a04e865
a04e866 a04e867 a04e868 a04e869 a04e8a0 a04e8a1 a04e8a2 a04e8a3
a04e8a4 a04e8a5 a04e8a6 a04e8a7 a04e8a8 a04e8a9 a04e8e0 a04e8e1
a04e8e2 a04e8e3 a04e8e4 a04e8e5 c04e821 c04e822 d04e821 d04e822
d04e823 d04e824 d04e825 d04e826 d04e827 d04e828 d04e829 d04e860
d04e861 d04e862 d04e863 8004e821 8004e822 700f011 904cf9a3 904cf9a4
904cf9a5 904cf9a6 904cf9a7 904cf9a8 904cf9a9 904cf9e0 904cf9e1 904cf9e2
904cf9e3 904cf9e4 904cf9e5 904cf9e6 904cf9e7 904cf9e8 904cf9e9 904cfa20
904cfa21 904cfa22 904cfa23 904cfa24 904cfa25 904cfa26 904cfa27 904cfa28
904cfa29 904cfa60 700f011
</a>
    </comp>
    <comp lib="0" loc="(630,240)" name="Pin">
      <a name="facing" val="west"/>
      <a name="output" val="true"/>
      <a name="width" val="32"/>
      <a name="labelloc" val="east"/>
    </comp>
  </circuit>
</project>
